As semiconductor devices become more highly integrated, very fine patterns may be formed on the semiconductor substrate. As part of the fabrication process, gaps or holes are often formed in these very fine patterns such as, for example, the contact holes that may be formed during the manufacture of various semiconductor memory devices. As the size of the pattern is reduced, the aspect ratio of the gaps in the pattern (the ratio of the gap height to the gap length) typically is increased. As this aspect ratio increases, it may become more difficult to satisfactorily fill the gap in subsequent steps of the manufacturing process.
In many cases, various of the gaps or holes in the pattern are filled with an insulating material such as an interlayer insulator. Various techniques have been used in an effort to fill gaps in fine semiconductor patterns with insulating interlayer materials. For example, in one known technique, a boron phosphor silicate glass (BPSG) is deposited (as the insulating material) on a substrate on which the fine pattern has already been formed, and a reflow process is performed on the BPSG layer at a temperature of 830° C. or more. During the reflow process, the BPSG may flow into and fill the gaps in the pattern. However, the high temperature applied to the device during the reflow process may cause thermal damage to the substrate.
As another example, it is known that a tetraethylorthosilicate (TEOS) or an undoped silicate glass (USG) may be deposited as an insulating interlayer on a semiconductor substrate to fill the gaps in a fine pattern. The TEOS or the USG may be deposited, for example, using a high-density plasma enhanced chemical vapor deposition (HDP-CVD) process. However, the TEOS or the USG may have a strong tendency to form a void or seam during the deposition process, and thus may not fully fill the gaps in the fine pattern.
As yet another example, a spin-on-glass (SOG) composition has been suggested as an insulating interlayer material as disclosed in Korean Publication Patent No. 2003-34328. In particular, polysilazane may be dissolved into an organic solvent, and the polysilazane solution may then be supplied onto the surface of a spinning wafer to form the SOG layer on the wafer. The solvent component may thereafter be removed from the SOG layer using, for example, a soft baking process. A hard baking process may then be performed on the SOG layer in an oxidizing atmosphere to form the silicon oxide layer on the wafer. Since the SOG is coated on the substrate in a liquid state, the gap fill characteristic of the material and the aspect ratio of the pattern may be improved.
The hard baking process which is carried out during the formation of the SOG layer may facilitate removal of elements such as, for example, hydrogen which may be present in the SOG layer that is initially deposited on the substrate. However, when the SOG layer is formed on a pattern that has very fine gaps, it may be difficult to supply adequate oxygen adjacent the bottom surfaces of the gaps in the pattern during the hard baking process. If sufficient oxygen is not supplied in this region during the hard baking process, the hard baking process may fail to remove extraneous elements, such as hydrogen, from the SOG layer. If sufficient of these elements remain, they may cause one or more voids to form in the silicon oxide layer (i.e., the silicon oxide layer may be porous). When a porous silicon oxide layer that includes a plurality of voids is etched and/or cleaned during subsequent processing steps, portions of the silicon oxide layer adjacent to the voids may etch away at a faster rate than do other non-porous portions of the silicon oxide layer.
For example, during the manufacture of a semiconductor memory device, a plurality of bit lines may be formed on a semiconductor substrate. When a silicon oxide layer is formed between the bit lines using the conventional SOG deposition process described above, the silicon oxide layer formed by the SOG process may be porous in the vicinity of the bottom portion of the gap between the bit lines. When the silicon oxide layer is etched away during subsequent processing step(s) in order to form a contact hole between the bit lines, one or more voids in the porous silicon oxide layer may appear along the lower inner surface of the contact hole. When a cleaning solution is thereafter supplied to the substrate for cleaning the by-products of the etching process, the portion of the contact hole around the exposed void may tend to be quickly etched away due to an etching component in the cleaning solution as compared with other portions of the contact hole.
FIG. 1 is a cross-sectional view illustrating a contact hole which may result when the above-described conventional process is used to form the contact holes. As shown in FIG. 1, a silicon oxide layer 11 is provided on a semiconductor substrate. The silicon oxide layer 11 includes porous portions 10. As shown in FIG. 1, these porous portions 10 of the silicon oxide layer 11 may etch away more quickly during, for example, a cleaning process that is part of the process for forming the contact hole as compared with other portions of the silicon oxide layer 11. As a result, the surface profile of the porous portions 10 of the silicon oxide layer 11 may be very rough (which is sometimes referred to as a “bad” profile), while the surface profile of the remaining portions of the contact hole 12 may be relatively smooth (which is sometimes referred to as a “good” profile). As shown in FIG. 1, the portion of the contact hole having a “bad” profile may tend to be concentrated at the lower portions of the contact hole 12. This indicates that it is the lower portion of the silicon oxide layer 11 that primarily includes the porous areas.
The above described over-etching of the porous portions of the silicon oxide layer may cause a “penetration hole” to form between adjacent contact holes. During a subsequent step in the manufacturing process, a conductive layer is formed in the contact holes. If a penetration hole exists in the silicon oxide layer that separates adjacent contact holes, the penetration hole may fill with the conductive material. If this occurs, the conductive layer acts to electrically connect the two contact holes, thereby generating a bridge failure in the semiconductor memory device.